R10000 Microprocessor User's Manual
The JTAG interface is implemented according to the standard IEEE 1149.1 test access port protocol specifications.
The JTAG interface accesses the JTAG controller and instruction register as well as a boundary scan register. The JTAG operation does not require DCOk to be asserted or SysClk to be running; however, if DCOk is asserted the SysClk must run at the specified minimum frequency or the core logic may get damaged. (See page 189 of the Errata.)
Chapter Contents
- 11.1 - Test Access Port (TAP)
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- 11.2 - Instruction Register
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- 11.3 - Bypass Register
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- 11.4 - Boundary Scan Register
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Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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